library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity preCalculatorB is
port(
    B	: in std_logic_vector(31 downto 0);
	Op	: in std_logic_vector(3 downto 0);
    inB	: out std_logic_vector(31 downto 0);
    Cin	: out std_logic
  );
end preCalculatorB;

architecture rtl of preCalculatorB is
signal ctrl : std_logic;
begin
	ctrl <= (not Op(3) and not Op(2) and Op(1));
	inB <= B xor (31 downto 0 => ctrl);
	Cin <= ctrl;
end architecture rtl;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity preCalculatorA is
port(
    A	: in std_logic_vector(31 downto 0);
	Op	: in std_logic_vector(3 downto 0);
    inA: out std_logic_vector(31 downto 0)
  );
end preCalculatorA;

architecture rtl of preCalculatorA is
signal ctrl:std_logic;
begin
	ctrl <= (Op(3) and Op(2) and Op(1));
	inA <= A xor (31 downto 0 => ctrl);
end architecture rtl;
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